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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Introduction
The Agere Systems Inc. L9216 is a subscriber line interface circuit (SLIC) that is optimized for shortloop, power-sensitive applications. This device provides the complete set of line interface functionality, including power ringing needed to interface to a subscriber loop. This device has the capability to operate with a VCC supply of 3.3 V or 5 V and is designed to minimize external components required at all device interfaces.
Applications
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Voice over Internet Protocol (VoIP) Cable Modems Terminal Adapters (TA) Wireless Local Loop (WLL)
Telcordia TechnologiesTM GR-909 Access
Network Termination (NT) Key Systems
Features
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Description
This device is optimized to provide battery feed, ringing, and supervision on short-loop plain old telephone service (POTS) loops. This device provides power ring to the subscriber loop through amplification of a low-voltage input. It provides forward and reverse battery feed states, onhook transmission, a low-power scan state, ground start (tip open), and a forward disconnect state. The device requires a VCC and battery to operate. VCC may be either a 5 V or a 3.3 V supply. The ringing signal is derived from the high-voltage battery. A battery switch is included to allow for use of a lowervoltage battery in the off-hook mode, thus minimizing short-loop off-hook power. Loop closure, ring trip, and ground start detectors are available. The loop closure detector has a fixed threshold with hysteresis. The ring trip detector requires a single-pole filter, thus minimizing external components required. The dc current limit is set and fixed by a logic controllable pin. Ground or open is applied to this pin set the current limit at the low or high value. The device is offered with two gain options. This allows for an optimized codec interface, with minimal external components regardless of whether a firstgeneration or a programmable third-generation codec is used.
Onboard ringing generation Three ringing input options: -- Sine wave -- PWM -- Logic level square wave Flexible VCC options: -- 5 V or 3.3 V VCC -- No -5 V required Battery switch to minimize off-hook power Eight operating states: -- Scan mode for minimal power dissipation -- Forward and reverse battery active -- On-hook transmission states -- Ground start (tip open) -- Ring mode -- Disconnect mode Ultralow on-hook power: -- 27 mW scan mode -- 41 mW active mode Two SLIC gain options to minimal external components in codec interface Loop start, ring trip, and ground start detectors Software-controllable dual current-limit option 28-pin PLCC package 48-pin MLCC package
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Table of Contents
Contents Page Contents Page
Introduction..................................................................1 Features ....................................................................1 Applications...............................................................1 Description ................................................................1 Features ......................................................................4 Description...................................................................4 Architecture Diagram...................................................7 Pin Information ............................................................8 Operating States .......................................................10 State Definitions ........................................................11 Forward Active ........................................................11 Reverse Active........................................................11 Scan........................................................................11 On-Hook Transmission--Forward Battery ..............11 On-Hook Transmission--Reverse Battery ..............11 Disconnect ..............................................................11 Ring.........................................................................11 Ground Start ...........................................................11 Thermal Shutdown..................................................12 Absolute Maximum Ratings (@ TA = 25 C) ..............12 Electrical Characteristics ...........................................13 Test Configurations ...................................................20 Applications ...............................................................22 Power Control .........................................................22 dc Loop Current Limit..............................................23 Overhead Voltage ...................................................23 Active Mode .........................................................23 Scan Mode ...........................................................23 On-Hook Transmission Mode...............................23 Ring Mode............................................................24 Loop Range ............................................................24 Battery Reversal Rate .............................................24 Supervision................................................................24 Loop Closure...........................................................24 Ring Trip .................................................................24 Tip or Ring Ground Detector ...................................24 Power Ring .............................................................25 Sine Wave Input Signal and Sine Wave Power Ring Signal Output .................................26 PWM Input Signal and Sine Wave Power Ring Signal Output.............................................28 5 V VCC Operation ................................................29 3.3 V VCC Operation .............................................30 Square Wave Input Signal and Trapezoidal Power Ring Signal Output .................................30
ac Applications ......................................................... 32 ac Parameters........................................................ 32 Codec Types .......................................................... 32 First-Generation Codecs ..................................... 32 Third-Generation Codecs .................................... 32 ac Interface Network .............................................. 32 Design Examples ................................................... 34 First-Generation Codec ac Interface Network--Resistive Termination ...................... 34 Example 1, Real Termination .............................. 34 First-Generation Codec ac Interface Network--Complex Termination ....................... 37 Complex Termination Impedance Design Example............................................................ 37 ac Interface Using First-Generation Codec ......... 37 Transmit Gain...................................................... 38 Receive Gain....................................................... 39 Hybrid Balance .................................................... 39 Blocking Capacitors ............................................ 40 Third-Generation Codec ac Interface Network--Complex Termination ....................... 42 Outline Diagrams...................................................... 44 28-Pin PLCC .......................................................... 44 48-Pin MLCC.......................................................... 45 48-Pin MLCC, JEDEC MO-220 VKKD-2................ 46 Ordering Information ................................................ 47
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Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC w/ Ground Start
Table of Contents (continued)
Figures Page Tables Page
Figure 1. Architecture Diagram ...................................7 Figure 2. 28-Pin PLCC ...............................................8 Figure 3. 48-Pin MLCC................................................8 Figure 4. Basic Test Circuit ......................................20 Figure 5. Metallic PSRR ...........................................21 Figure 6. Longitudinal PSRR ....................................21 Figure 7. Longitudinal Balance .................................21 Figure 8. ac Gains ....................................................21 Figure 9. Ringing Waveform Crest Factor = 1.6 .......25 Figure 10. Ringing Waveform Crest Factor = 1.2 .....25 Figure 11. Ring Mode Typical Operation ..................26 Figure 12. RINGIN Operation ....................................27 Figure 13. L9215/16 Ringing Input Circuit Selection Table for Square Wave and PWM Inputs .......................................................28 Figure 14. Modulation Waveforms ............................29 Figure 15. 5 V PWM Signal Amplitude .....................29 Figure 16. Ringing Output on RING, with VCC = 5 V .................................................29 Figure 17. 3.3 V PWM Signal Amplitude ..................30 Figure 18. Ringing Output on RING, with VCC = 3.1 V ..............................................30 Figure 19. Square Wave Input Signal and Trapezoidal Power Ring Signal Output ...30 Figure 20. Crest Factor vs. Battery Voltage .............31 Figure 21. Crest Factor vs. R (k) ...........................31 Figure 22. ac Equivalent Circuit ................................35 Figure 23. Agere T7504 First-Generation Codec Resistive Termination ..............................35 Figure 24. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown) ....................................................38 Figure 25. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex Termination Impedance ...........40 Figure 26. Agere T7504 First-Generation Codec Complex Termination ..............................40 Figure 27. Third-Generation Codec ac Interface Network; Complex Termination ...............42
Table 1. Pin Descriptions .......................................... 9 Table 2. Control States ............................................. 10 Table 3. Supervision Coding ................................... 10 Table 4. Recommended Operating Characteristics .......................................... 12 Table 5. Thermal Characteristics.............................. 12 Table 6. Environmental Characteristics .................... 13 Table 7. 5 V Supply Currents ................................... 13 Table 8. 5 V Powering .............................................. 13 Table 9. 3.3 V Supply Currents ............................... 14 Table 10. 3.3 V Powering ......................................... 14 Table 11. 2-Wire Port .............................................. 15 Table 12. Analog Pin Characteristics ..................... 16 Table 13. ac Feed Characteristics .......................... 17 Table 14. Logic Inputs and Outputs (VCC = 5 V) ..... 18 Table 15. Logic Inputs and Outputs (VCC = 3.3 V) .. 18 Table 16. Ground Start ............................................ 18 Table 17. Ringing Specifications ............................. 19 Table 18. Ring Trip .................................................. 19 Table 19. Typical Active Mode On- to Off-Hook Tip/Ring Current-Limit Transient Response ................................................ 23 Table 20. FB1 and FB2 Values vs. Typical Ramp Time ......................................................... 24 Table 21. Onset of Power Ringing Clipping VCC = 5 V, Cinput = 0.47 F ................... 27 Table 22. Onset of Power Ringing Clipping VCC = 3.1 V, Cinput = 0.47 F ................ 27 Table 23. Signal and Component Selection Chart ... 28 Table 24. Parts List L9216; Agere T7504 FirstGeneration Codec Resistive Termination; Nonmeter Pulse Application ................... 36 Table 25. Parts List L9216; Agere T7504 FirstGeneration Codec Complex Termination; Meter Pulse Application ........................... 41 Table 26. Parts List L9216; Agere T8536 Third-Generation Codec ac and dc Parameters; Fully Programmable ...... 43
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
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Features
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Onboard balanced ringing generation: -- No ring relay -- No bulk ring generator required -- 15 Hz to 70 Hz ring frequency supported -- Sine wave input-sine wave output -- PWM input-sine wave output -- Square wave input-trapezoidal output Power supplies requirements: -- VCC talk battery and ringing battery required -- No -5 V supply required -- No high-voltage positive supply required Flexible Vcc options: -- 5 V or 3.3 V VCC operation -- 5 V or 3.3 V VCC interchangeable and transparent to users Battery switch via logic control: -- Minimize off-hook power dissipation Minimal external components required Eight operating states: -- Forward active, VBAT2 applied -- Polarity reversal active, VBAT2 applied -- On-hook transmission, VBAT1 applied -- On-hook transmission polarity reversal, VBAT1 applied -- Ground start -- Scan -- Forward disconnect -- Ring mode Unlatched parallel data control interface Ultralow SLIC power: -- Scan 37 mW (VCC = 5 V) -- Forward/reverse active 54 mW (VCC = 5 V) -- Scan 27 mW (VCC = 3.3 V) -- Forward/reverse active 41 mW (VCC = 3.3 V) Supervision: -- Loop start, fixed threshold with hysteresis -- Ring trip, single-pole ring trip filtering, fixed threshold as a function of battery voltage -- Ring current for ground start applications, useradjustable threshold
Adjustable current limit: -- 25 mA or 40 mA via ground or open to control input Overhead voltage: -- Clamped typically <51 V differentially -- Clamped maximum <56.5 V single-ended Thermal shutdown protection with hysteresis Longitudinal balance: -- Telcordia Technologies GR-909 balance ac interface: -- Two SLIC gain options to minimize external components required for interface to first- or third-generation codecs -- Sufficient dynamic range for direct coupling to codec output 28-pin PLCC/48-pin MLCC package 90 V CBIC-S technology
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Description
The L9216 is designed to provide battery feed, ringing, and supervision functions on short plain old telephone service (POTS) loops. This device is designed for ultralow power in all operating states. The L9216 offers eight operating states. The device assumes uses of a lower-voltage talk battery, a highervoltage ringing battery, and a VCC supply. The L9216 requires only a positive VCC supply. No -5 V supply is needed. The L9216 can operate with a VCC of either 5 V or 3.3 V, allowing for greater user flexibility. The choice of VCC voltage is transparent to the user; the device will function with either supply voltage connected. Two batteries are used: 1. A high-voltage ring battery (VBAT1). VBAT1 is a maximum -75 V. VBAT1 is used for power ring signal amplification and for scan, on-hook transmission, and ground start modes. This supply is current limited to approximately the maximum power ringing current, typically 50 mA. 2. A lower-voltage talk battery (VBAT2). VBAT2 is used for active mode powering.
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Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
The device offers a ground start mode. In this mode, the tip drive amplifier is turned off. The device presents a high impedance (>100 k) to PT and a current-limited battery (VBAT1) to PR. VBAT1 is clamped to less than 56.5 V in this mode as PR. A ring current detector for ring ground detection is included for ground start applications. The threshold is user programmable via external resistors. See the Applications section of this data sheet for more information on supervision functions. Output pin RGDET indicates current flowing in the ring lead. Both the ring trip and loop closure supervision functions are included. The loop closure has a fixed typical 10.5 mA on- to off-hook threshold in the active mode and a fixed 11.5 mA on- to off-hook threshold from the scan mode. In either case, there is a 2 mA hysteresis. The ring trip detector requires only a single-pole filter at the input, minimizing external components. The ring trip threshold at a given battery voltage is fixed. Typical ring trip threshold is 42.5 mA for a -70 V VBAT1. Upon reaching the thermal shutdown temperature, the device will enter an all-off mode. Upon cooling, the device will re-enter the state it was in prior to thermal shutdown. Hysteresis is built in to prevent oscillation. Longitudinal balance is consistent with North American GR-909 requirements. Specifications are given in Table 12. Data control is via a parallel unlatched control scheme. The dc current limit is fixed to either 25 mA or 40 mA depending if ground or open is applied to the VPROG current-limit programming pin. Programming accuracy is 8%. Circuitry is added to the L9216 to minimize the inrush of current from the VCC supply and to the battery supply during an on- to off-hook transition, thus saving in power supply design cost. See the Applications section of this data sheet for more information. Overhead in the active modes (VBAT2 applied) is fixed to approximately 6.0 V is achieved. This is adequate for a 3.14 dBm overload into 900 . Transmit and receive gains have been chosen to minimize the number of external components required in the SLIC-codec ac interface, regardless of the choice of codec.
Description (continued)
Forward and reverse battery active modes are used for off-hook conditions. Since this device is designed for short-loop applications, the lower-voltage VBAT2 is applied during the forward and reverse active states. Battery reversal is quiet, without breaking the ac path. Rate of battery reversal may be ramped to control switching time. The magnitude of the overhead voltage in the forward and reverse active modes has a typical default value of 6.0 V, allowing for an undistorted signal of 3.14 dBm into 900 . This overhead is fixed. The ring trip detector is turned off during active modes to conserve power. Because on-hook transmission is not allowed in the scan mode, an on-hook transmission mode is defined. This mode is functionally similar to the active mode, except the tip ring voltage is derived from the higher VBAT1 rather than VBAT2. In the on-hook transmission modes with a primary battery whose magnitude is greater than a nominal 51 V, the magnitude of the tip to ground and ring to ground voltage is clamped at less than 56.5 V. To minimize on-hook power, a low-power scan mode is available. In this mode, all functions except off-hook supervision are turned off to conserve power. On-hook transmission is not allowed in the scan mode. In the scan mode with a primary battery whose magnitude is greater than a nominal 51 V, the magnitude of the tip to ground and ring to ground voltage is clamped at less than 56.5 V. A forward disconnect mode is provided, where all circuits are turned off and power is denied to the loop. The device offers a ring mode, in which a power ring signal is provided to the tip/ring pair. During the ring mode, a user-supplied low-voltage ring signal (ac-coupled) is input to the device's RINGIN input. This signal is amplified to produce the power ring signal. This signal may be a sine wave or filtered square wave to produce a sine wave on trapezoidal output. Ring trip detector and common-mode current detector are active during the ring mode. This feature eliminates the need for a separate external ring relay, associated external circuitry, and a bulk ringing generator. See the Applications section of this data sheet for more information.
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
performance, it is best to operate the codec at a higher gain level. If the SLIC then provides a high gain, the SLIC output may be saturated causing clipping distortion of the signal at tip and ring. To avoid this situation, with a higher gain SLIC, external resistor dividers are used. These external components are not necessary with the lower gain offered by the L9216. See the Applications section of this data sheet for more information. The L9216 is internally referenced to 1.5 V. This reference voltage is output at the VREF output of the device. The SLIC output VITR is also referenced to 1.5 V; therefore, it must be ac coupled to the codec input. However, the SLIC inputs RCVP/RCVN are floating inputs. If there is not feedback from RCVP/RCVN to VITR, RCVP/RCVN may be directly coupled to the codec output. If there is feedback from RCVP/RCVN to VITR, RCVP/RCVN must be ac coupled to the codec output. The L9216 is packaged in a 28-pin PLCC package and an ultrasmall 48-pin MLCC package. Use L9216A for gain of eight applications and L9216G for gain of two applications.
Description (continued)
The L9216 uses a voltage feed-current sense architecture; thus, the transmit gain is a transconductance. The L9216 transconductance is set via a single external resistor, and this device is designed for optimal performance with a transconductance set at 300 V/A. The L9216 offers an option for a single-ended to differential receive gain of either 8 or 2. These options are mask programmable at the factory and are selected by choice of code. A receive gain of 8 is more appropriate when choosing a first-generation type codec where termination impedance, hybrid balance, and overall gains are set by external analog filters. The higher gain is typically required for synthesization of complex termination impedance. A receive gain of 2 is more appropriate when choosing a third-generation type codec. Third-generation codecs will synthesize termination impedance and set hybrid balance and overall gains. To accomplish these functions, third-generation codecs typically have both analog and digital gain filters. For optimal signal to noise
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Architecture Diagram
AGND VCC BGND VBAT2 VBAT1 VPROG NSTAT RTFLT DCOUT
VREF VITR B = 20 POWER
CURRENT LIMIT AND INRUSH CONTROL
RING TRIP
LOOP CLOSURE AAC TXI ITR - VTX OUT AX + (ITR/306) VREF X1 CF2 1.5 V BAND-GAP REFERENCE VTX RECTIFIER COMMONMODE CURRENT DETECTOR ICM RGDET
RFT PT ITR 18 +1
- + X1 CF1 FB2 FB1 - GAIN + - VREG ac INTERFACE 9216A GAIN = 4 9216G GAIN = 1 PARALLEL DATA INTERFACE RCVN RCVP VREG
TIP/RING CURRENT SENSE ITR PR
RFR 18 -1
+
RINGING 27.5x
RINGIN
B0
B1
B2 12-3530.E (F)
Figure 1. Architecture Diagram
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Pin Information
NSTAT
RCVN
RCVP
VITR
VTX 27
4 RINGIN DCOUT VPROG CF2 CF1 RTFLT VREF 5 6 7 8 9 10 11 12 AGND
3
2
1
28
26 25 24 23
ITR B0 B1 B2 PR PT FB1 FB2 22 21 20 19 18 ICM
L9216 28-PIN PLCC
13 VCC
14 VBAT1
15 VBAT2
16 BGND
TXI
17 RGDET
12-3558.d (F)
Figure 2. 28-Pin PLCC
NSTAT
RCVN
RCVP
VITR
VTX
NC
NC
NC
NC
ITR
TXI
48 47 46 45 44 43 42 41 40 39 38 37 RINGIN NC NC NC NC DCOUT VPROG NC CF2 CF1 NC RTFLT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VBAT1 AGND VBAT2 RGDET BGND VREF ICM NC NC NC VCC NC L9216A/G 48-PIN MLCC 36 35 34 33 32 31 30 29 28 27 26 25 NC B0 B1 B2 NC PR NC PT NC NC FB1 FB2
Figure 3. 48-Pin MLCC
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NC
Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Pin Information (continued)
Table 1. Pin Descriptions 28-Pin PLCC 1 48-Pin MLCC 43 Symbol NSTAT Type O Name/Function Loop Closure Detector Output--Ring Trip Detector Output. When low, this logic output indicates that an off-hook condition exists or ringing is tripped. Transmit ac Output Voltage. Output of internal AAC amplifier. This output is a voltage that is directly proportional to the differential ac tip/ring current. Receive ac Signal Input (Noninverting). This high-impedance input controls the ac differential voltage on tip and ring. This node is a floating input. Receive ac Signal Input (Inverting). This high-impedance input controls the ac differential voltage on tip and ring. This node is a floating input. Power Ring Signal Input. ac-couple to a sine wave or lower crest factor low-voltage ring signal. The input here is amplified to provide the full power ring signal at tip and ring. This signal may be applied continuously, even during nonringing states. dc Output Voltage. This output is a voltage that is directly proportional to the absolute value of the differential tip/ring current. This is used to set ring trip threshold. Current-Limit Program Input. Connect ground to this pin to set current-limit to 25 mA, float to this pin to set current limit to 40 mA. Filter Capacitor. Connect a capacitor from this node to ground. Filter Capacitor. Connect a capacitor from this node to CF2. Ring Trip Filter. Connect this lead to DCOUT via a resistor and to AGND with a capacitor to filter the ring trip circuit to prevent spurious responses. A single-pole filter is needed. SLIC Internal Reference Voltage. Output of internal 1.5 V reference voltage. Analog Signal Ground. Analog Power Supply. User choice of 5 V or 3.3 V nominal power or supply. Battery Supply 1. High-voltage battery. Battery Supply 2. Lower-voltage battery. Battery Ground. Ground return for the battery supplies. No Connection.
2
45
VITR
O
3
47
RCVP
I
4
48
RCVN
I
5
1
RINGIN
I
6
6
DCOUT
O
7 8 9 10
7 9 10 12
VPROG CF2 CF1 RTFLT
I -- -- --
11 12 13 14 15 16 --
13 15 16 19 20 22 2, 3, 4, 5, 8, 11, 14, 17, 18, 21, 27, 28, 30, 32, 36, 37, 39, 42, 44, 46 23
VREF AGND VCC VBAT1 VBAT2 BGND NC
O GND PWR PWR PWR GND --
17
RGDET
O
18
24
ICM
I
Ring Ground Detect. When high, this open collector output indicates the presence of a ring ground or a tip ground. This supervision output may be used in ground key, ground start or commonmode fault detection applications. Common-Mode Current Sense. To program tip or ring ground sense threshold, connect a resistor to VCC and connect a capacitor to AGND to filter 50/60 Hz. If unused, the pin is connected to ground. 9
Agere Systems Inc.
L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Pin Information (continued)
Table 1. Pin Descriptions (continued) 28-Pin PLCC 19 48-Pin MLCC 25 Symbol FB2 Type -- Name/Function Polarity Reversal Slowdown Capacitor. Connect a capacitor from this node to ground for controlling rate of battery reversal. If ramped battery reversal is not desired, this pin is left open. Polarity Reversal Slowdown Capacitor. Connect a capacitor from this node to ground for controlling rate of battery reversal. If ramped battery reversal is not desired, this pin is left open. Protected Tip. The output drive of the tip amplifier and input to the loop sensing circuit. Connect to loop through overvoltage and overcurrent protection. Protected Ring. The output drive of the ring amplifier and input to the loop sensing circuit. Connect to loop through overvoltage and overcurrent protection. State Control Input. These pins have an internal 110 k pull-down.
20
26
FB1
--
21
29
PT
I/O
22
31
PR
I/O
23 24 25 26
33 34 35 38
B2 B1 B0 ITR
Id I
d
Id I Transmit Gain. Input to AX amplifier. Connect a 4.75 k resistor from this node to VTX to set transmit gain. Gain shaping for termination impedance with a first-generation codec is also achieved with a network from this node to VTX. ac Output Voltage. Output of internal AX amplifier. The voltage at this pin is directly proportional to the differential tip/ring current. ac/dc Separation. Input to internal AAC amplifier. Connect a 0.1 F capacitor from this pin to VTX.
27 28
40 41
VTX TXI
O I
Operating States
Table 2. Control States B0 1 1 1 1 0 0 0 0 B1 1 0 1 0 0 1 0 1 B2 0 0 1 1 1 1 0 0 State Forward active Reverse active On-hook transmission forward battery On-hook transmission reverse battery Ground start Scan Disconnect, device will power up in this state Ring
Table 3. Supervision Coding NSTAT RGDET 0 = off-hook or ring trip or TSD. 0 = no ring or tip ground. 1 = on-hook and no ring trip and no TSD or DISCONNECT state. 1 = ring or tip ground.
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
On-Hook Transmission--Reverse Battery
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State Definitions
Forward Active
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Pin PR is positive with respect to PT. VBAT1 is applied to tip/ring drive amplifiers. Supervision circuits, loop closure, and commonmode detect are active. Ring trip detector is turned off to conserve power. On-hook transmission is allowed. The tip-to-ring on-hook differential voltage will be typically between -41 V and -49 V with a -70 V primary battery.
Pin PT is positive with respect to PR. VBAT2 is applied to tip/ring drive amplifiers. Loop closure and common-mode detect are active. Ring trip detector is turned off to conserve power. Overhead is set to nominal 6.0 V for undistorted transmission of 3.14 dBm into 900 .
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Reverse Active
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Disconnect
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Pin PR is positive with respect to PT. VBAT2 is applied to tip/ring drive amplifiers. Loop closure and common-mode detect are active. Ring trip detector is turned off to conserve power. Overhead is set to nominal 6.0 V for undistorted transmission of 3.14 dBm into 900 . The tip/ring amplifiers and all supervision are turned off. The SLIC goes into a high-impedance state. NSTAT is forced high (on-hook). Device will power up in this state.
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Scan
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Ring
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Except for loop closure, all circuits (including ring trip and common-mode detector) are powered down. On-hook transmission is disabled. Pin PT is positive with respect to PR, and VBAT1 is applied to tip/ring. The tip to ring on-hook differential voltage will be typicallybetween -44 V and -51 V with a -70 V primary battery.
Power ring signal is applied to tip and ring. Input waveform at RINGIN is amplified. Ring trip supervision and common-mode current supervision are active; loop closure is inactive. Overhead voltage is reduced to typically 4 V. Current is limited by saturation current of the amplifiers themselves, typically 100 mA at 125 C.
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On-Hook Transmission--Forward Battery
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Ground Start
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Tip drive amplifer is turned off. Device presents a high impedance (>100 k) to pin PT. Device presents a clamped (<56.5 V) current-limited battery (VBAT1) to PR. Output pin RGDET indicates current flowing in the ring lead.
Pin PT is positive with respect to PR. VBAT1 is applied to tip/ring drive amplifiers. Supervision circuits, loop closure, and commonmode detect are active. Ring trip detector is turned off to conserve power. On-hook transmission is allowed. The tip-to-ring on-hook differential voltage will be typically between -41 V and -49 V with a -70 V primary battery.
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Thermal Shutdown
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Not controlled via truth table inputs. NSTAT is forced low (off-hook) during this state. This mode is caused by excessive heating of the device, such as may be encountered in an extended power cross situation. 11
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Absolute Maximum Ratings (@ TA = 25 C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter dc Supply (VCC) Battery Supply (VBAT1) Battery Supply (VBAT2) Logic Input Voltage Logic Output Voltage Operating Temperature Range Storage Temperature Range Relative Humidity Range PT or PR Fault Voltage (dc) PT or PR Fault Voltage (10 x 1000 s) Ground Potential Difference (BGND to AGND) Symbol -- -- -- -- -- -- -- -- VPT, VPR VPT, VPR -- Min -0.5 -- -- -0.5 -0.5 -40 -40 5 VBAT - 5 VBAT - 15 -- Typ -- -- -- -- -- -- -- -- -- -- -- Max 7.0 -80 VBAT1 VCC + 0.5 VCC + 0.5 125 150 95 3 15 1 Unit V V V V V C C % V V V
Note: The IC can be damaged unless all ground connections are applied before, and removed after, all other connections. Furthermore, when powering the device, the user must guarantee that no external potential creates a voltage on any pin of the device that exceeds the device ratings. For example, inductance in a supply lead could resonate with the supply filter capacitor to cause a destructive overvoltage.
Table 4. Recommended Operating Characteristics Parameter 5 V dc Supplies (VCC) 3 V dc Supplies (VCC) High Office Battery Supply (VBAT1) Auxiliary Office Battery Supply (VBAT2) Operating Temperature Range Table 5. Thermal Characteristics Parameter Thermal Protection Shutdown (Tjc)
1
Min -- 3.13 -60 -12 -40
Typ 5.0 3.3 -70 -- 25
Max 5.25 -- -75 VBAT1 85
Unit V V V V C
Min 150 -- -- -- -- --
Typ 165 35.5 50.5 31.5 42.5 38
Max -- -- -- -- -- --
Unit C C/W C/W C/W C/W C/W
28-pin PLCC Thermal Resistance Junction to Ambient (JA)2: Natural Convection 2S2P Board Natural Convection 2S0P Board Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S2P Board Wind Tunnel 100 Linear Feet per Minute (LFPM) 2S0P Board 48-pin MLCC Thermal Resistance Junction to Ambient (JA)1, 2
1. This parameter is not tested in production. It is guaranteed by design and device characterization. 2. Airflow, PCB board layers, and other factors can greatly affect this parameter.
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Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Electrical Characteristics
Table 6. Environmental Characteristics Parameter Temperature Range Humidity Range1
1. Not to exceed 26 grams of water per kilogram of dry air.
Min -40 5
Typ -- --
Max 85 951
Unit C %RH
Table 7. 5 V Supply Currents VBAT1 = -70 V, VBAT2 = -21 V, VCC = 5 V. Parameter Supply Currents (scan state; no loop current): IVCC IVBAT1 IVBAT2 Supply Currents (forward/reverse active; no loop current, with or without PPM, VBAT2 applied): IVCC IVBAT1 IVBAT2 Supply Currents (on-hook transmission mode; no loop current, with or without PPM, VBAT1 applied): IVCC IVBAT1 IVBAT2 Supply Currents (disconnect mode): IVCC IVBAT1 IVBAT2 Supply Currents (ground start mode, no loop current): IVCC IVBAT1 IVBAT2 Supply Currents (ring mode; no load): IVCC IVBAT1 IVBAT2 Table 8. 5 V Powering VBAT1 = -70 V, VBAT2 = -21 V, VCC = 5 V. Parameter Power Dissipation (scan state; no loop current) Power Dissipation (forward/reverse active; no loop current, VBAT2 applied) Power Dissipation (on-hook transmission mode; no loop current, VBAT1 applied) Power Dissipation (disconnect mode) Power Dissipation (ground start mode) Power Dissipation (ring mode; no load) Min -- -- -- -- -- -- Typ 38 57 135 14 37 156 Max 46 64 165 23 -- 184 Unit mW mW mW mW mW mW Min -- -- -- Typ 4.30 0.24 3 Max 4.80 0.35 6 Unit mA mA A
-- -- --
5.95 25 1.2
7.0 85 1.40
mA A mA
-- -- -- -- -- -- -- -- -- -- -- --
6.0 1.5 1.5 2.7 15 3.5 4.0 0.24 2 5.9 1.8 2
7.0 1.9 6 3.75 110 25 -- -- -- 6.5 2.2 6
mA mA A mA A A mA mA A mA mA A
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Electrical Characteristics (continued)
Table 9. 3.3 V Supply currents VBAT1 = -70 V, VBAT2 = -21 V, VCC = 3.3 V. Parameter Supply Currents (scan state; no loop current): IVCC IVBAT1 IVBAT2 Supply Currents (forward/reverse active; no loop current, VBAT2 applied): IVCC IVBAT1 IVBAT2 Supply Currents (on-hook transmission mode; no loop current, VBAT1 applied): IVCC IVBAT1 IVBAT2 Supply Currents (disconnect mode): IVCC IVBAT1 IVBAT2 Supply Currents (ground start mode, no loop current): IVCC IVBAT1 IVBAT2 Supply Currents (ring mode; no load): IVCC IVBAT1 IVBAT2 Table 10. 3.3 V Powering VBAT1 = -70 V, VBAT2 = -21 V, VCC = 3.3 V. Parameter Power Dissipation (scan state; no loop current) Power Dissipation (forward/reverse active; no loop current, VBAT2 applied) Power Dissipation (on-hook transmission mode; no loop current, VBAT1 applied) Power Dissipation (disconnect mode) Power Dissipation (ground start mode) Power Dissipation (ring mode; no loop current) Min -- -- -- -- -- -- Typ 27 42 121 6.5 27 141 Max 36.5 53 151 15 -- 172 Unit mW mW mW mW mW mW Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ 3.2 0.24 3 4.8 25 1.2 4.9 1.5 1.5 1.8 8 2 3.1 0.24 2 4.70 1.8 2 Max 3.6 0.35 6 5.7 85 1.4 5.7 1.9 6 2.5 110 25 -- -- -- 5.4 2.2 6 Unit mA mA A mA A mA mA mA A mA A A mA mA A mA mA A
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Electrical Characteristics (continued)
Table 11. 2-Wire Port Parameter Tip or Ring Drive Current = dc + Longitudinal + Signal Currents Tip or Ring Drive Current = Ringing + Longitudinal Signal Current Longitudinal Current Capability per Wire (Longitudinal current is independent of dc loop current.) Ringing Current (RLOAD = 1386 + 40 F) Ringing Current Limit (RLOAD = 100 ) dc Loop Current--ILIM (VBAT2 applied, RLOOP = 100 ): VPROG = 0 VPROG = Open dc Current Variation dc Feed Resistance (does not include protection resistors) Open Loop Voltages: Scan Mode: |VBAT1| > 51 V |VTIP| - |VRING| PR to Battery Ground PT to Battery Ground OHT Mode: |VBAT1| > 51 V |VTIP| - |VRING| PR to Battery Ground PT to Battery Ground Active Mode: |PT - PR| - |VBAT2| Ring Mode: |PT - PR| - |VBAT1| Min 105 65 10 8.5 29 -- -- -- -- -- Typ -- -- -- 15 -- -- 25 40 -- 50 Max -- -- -- -- -- 50 -- -- 8 -- Unit mAp mAp mArms mArms mArms mAp mA mA %
44 -- -- 41 -- -- 5.75 --
51 -- -- 49 -- -- 6.25 4
-- 56.5 56.5 -- 56.5 56.5 6.75 --
V V V V V V V V
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Electrical Characteristics (continued)
Table 11. 2-Wire Port (continued) Parameter Loop Closure Threshold: Active/On-hook Transmission Modes Scan Mode Loop Closure Threshold Hysteresis: VCC = 5 V Active Mode VCC = 3.3 V Active Mode VCC = 5 V Ground Start Mode VCC = 3.3 V Ground Start Mode Longitudinal to Metallic Balance at PT/PR Test Method: Q552 (11/96) Section 2.1.2 and IEEE(R) 455: 300 Hz to 600 Hz 600 Hz to 3.4 kHz Metallic to Longitudinal (harm) Balance: 200 Hz to 1000 Hz 100 Hz to 4000 Hz PSRR 500 Hz--3000 Hz: VBAT1, VBAT2 VCC (5 V operation) Table 12. Analog Pin Characteristics Parameter TXI (input impedance) Output Offset (VTX) Output Offset (VITR) Output Drive Current (VTX) Output Drive Current (VITR) Output Voltage Swing: Maximum (VTX, VITR) Minimum (VTX) Minimum (VITR) Output Short-circuit Current Output Load Resistance Output Load Capacitance RCVN and RCVP: Input Voltage Range (VCC = 5 V) Input Voltage Range (VCC = 3.3 V) Input Bias Current Differential PT/PR Current Sense (DCOUT): Gain (PT/PR to DCOUT) Offset Voltage at ILOOP = 0 Min -- -- -- 300 10 AGND AGND + 0.25 AGND + 0.35 -- 10 -- 0 0 -- -- -20 Typ 100 -- -- -- -- -- -- -- -- -- 20 -- -- 0.05 67 -- Max -- 10 100 -- -- VCC VCC - 0.5 VCC - 0.4 50 -- -- VCC - 0.5 VCC - 0.3 -- -- 20 Unit k mV mV A A V V V mA k pF V V A V/A mV Min -- -- -- -- -- -- Typ 10.5 11.5 2 1 6 5 Max -- -- -- -- -- -- Unit mA mA mA mA mA mA
52 52 40 40 45 35
-- -- -- -- -- --
-- -- -- -- -- --
dB dB dB dB dB dB
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Electrical Characteristics (continued)
Table 13. ac Feed Characteristics Parameter ac Termination Total Harmonic Distortion (200 Hz--4 kHz)2: Off-hook On-hook Transmit Gain (f = 1004 Hz, 1020 Hz, current limit)3: PT/PR Current to VITR Receive Gain, f = 1004 Hz, 1020 Hz Open Loop: RCVP or RCVN to PT--PR (gain of 8 option, L9216A) RCVP or RCVN to PT--PR (gain of 2 option, L9216G) Gain vs. Frequency (transmit and receive)2 600 Termination, 1004 Hz, 1020 Hz Reference: 200 Hz--300 Hz 300 Hz--3.4 kHz 3.4 kHz--20 kHz 20 kHz--266 kHz Gain vs. Level (transmit and receive)2 0 dBV Reference: -55 dB to +3.0 dB Idle-channel Noise (tip/ring) 600 Termination: Psophometric C-Message 3 kHz Flat Idle-channel Noise (VTX) 600 Termination: Psophometric C-Message 3 kHz Flat Impedance1 Min 150 -- -- 300 - 3% 7.76 1.94 Typ 600 -- -- 300 8 2 Max 1400 0.3 1.0 300 + 3% 8.24 2.06 Unit % % V/A -- --
-0.3 -0.05 -3.0 -- -0.05 -- -- -- -- -- --
0 0 0 -- 0 -82 8 -- -82 8 --
0.05 0.05 0.05 2.0 0.05 -77 13 20 -77 13 20
dB dB dB dB dB dBmp dBrnC dBrn dBmp dBrnC dBrn
1. Set externally either by discrete external components or a third- or fourth-generation codec. Any complex impedance R1 + R2 || C between 150 and 1400 can be synthesized. 2. This parameter is not tested in production. It is guaranteed by design and device characterization. 3. VITR transconductance depends on the resistor from ITR to VTX. This gain assumes an ideal 4750 , the recommended value. Positive current is defined as the differential current flowing from PT to PR.
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Electrical Characteristics (continued)
Table 14. Logic Inputs and Outputs (VCC = 5 V) Parameter Input Voltages: Low Level High Level Input Current: Low Level (VCC = 5.25 V, VI = 0.4 V) High Level (VCC = 5.25 V, VI = 2.4 V) Output Voltages (open collector with internal pull-up resistor): Low Level (VCC = 4.75 V, IOL = 200 A) High Level (VCC = 4.75 V, IOH = -20 A) Table 15. Logic Inputs and Outputs (VCC = 3.3 V) Parameter Input Voltages: Low Level High Level Input Current: Low Level (VCC = 3.46 V, VI = 0.4 V) High Level (VCC = 3.46 V, VI = 2.4 V) Output Voltages (open collector with internal 60 k pull-up resistor): Low Level (VCC = 3.13 V, IOL = 200 A) High Level (VCC = 3.13 V, IOH = -5 A) Table 16. Ground Start Parameter Tip Open Mode: Tip Input Impedance Detector Accuracy Detection Min 150 -- 50 Typ -- -- -- Max -- 20 -- Unit k % ms Symbol VIL VIH IIL IIH VOL VOH Min -0.5 2.0 -- -- 0 2.2 Typ 0.2 2.5 -- -- 0.2 -- Max 0.5 VCC 50 50 0.5 VCC Unit V V A A V V Symbol VIL VIH IIL IIH VOL VOH Min -0.5 2.0 -- -- 0 2.4 Typ 0.4 2.4 -- -- 0.2 -- Max 0.7 VCC 50 50 0.4 VCC Unit V V A A V V
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Electrical Characteristics (continued)
Table 17. Ringing Specifications Parameter RINGIN (This input is ac coupled through 0.47 F.): Input Voltage Swing Input Impedance Ring Signal Isolation: PT/PR to VITR Ring Mode Ring Signal Isolation: RINGIN to PT/PR Nonring Mode Ringing Voltage (5 REN 1380 + 40 F load, 100 loop, 2 x 50 protection resistors, -70 V battery) Ringing Voltage (3 REN 2310 + 24 F load, 250 loop, 2 x 50 protection resistors, -70 V battery) Ring Signal Distortion: 5 REN 1380 , 40 F Load, 100 Loop 3 REN 2310 , 24 F Load, 250 Loop Differential Gain: RINGIN to PT/PR--No Load Table 18. Ring Trip Parameter Ring Trip (NSTAT = 0): Loop Resistance (total) High Battery Ring Trip (NSTAT = 1): Loop Resistance (total) High Battery Trip Time (f = 20 Hz) Ringing will not be tripped by the following loads:
s s
Min 0 -- --
Typ -- 100 60
Max VCC -- --
Unit V k dB
--
80
--
dB
40 40
-- --
-- --
Vrms Vrms
-- -- --
3 3 55
-- -- --
% % --
Min 100 -- --
Typ -- -- --
Max 600 10 100
Unit k ms
10 k resistor in parallel with a 6 F capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz. 100 resistor in series with a 2 F capacitor applied across tip and ring. Ring frequency = 17 Hz to 23 Hz.
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Test Configurations
RTFLT 0.1 F 383 k DCOUT 30 TIP RLOOP 100 /600 30 RING PT L9216 BASIC TEST CIRCUIT PR
RINGIN 0.47 F
RINGIN
26.7 k RCVP RCVN 0.1 F VITR 0.1 F TXI VTX 4750 ITR FB2 FB1 B0 CF1 B1 B2 B0 B1 B2 VITR RCV RCV
60.4 k 69.8 k
VPROG VREF
0.1 F CF2 0.1 F VBAT2 VBAT1 BGND VCC AGND ICM RGDET NSTAT
0.1 F 0.1 F VBAT2 VBAT1 VCC
0.1 F
114 k
0.1 F
VCC
12-3531.h (F)
Figure 4. Basic Test Circuit
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Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Test Configurations (continued)
VBAT OR VCC 100 4.7 F VS VBAT OR VCC TIP DISCONNECT BYPASS CAPACITOR VS 100 F TIP 368 368
+
VM BASIC TEST CIRCUIT RING
-
100 F
+
600 VT/R
BASIC TEST CIRCUIT
LONGITUDINAL BALANCE = 20log
VS VM
12-2584.c (F)
-
RING
Figure 7. Longitudinal Balance
VS VT/R
12-2582.c (F)
PSRR = 20log
Figure 5. Metallic PSRR
+
VBAT OR VCC 100 4.7 F VS VBAT OR VCC 67.5 TIP 10 F + VM - 67.5 56.3 RING 10 F PSRR = 20log VS VM
12-2583.b (F)
PT 600 VT/R BASIC TEST CIRCUIT PR RCV
VITR
DISCONNECT BYPASS CAPACITOR
-
RCV VS
GXMT = GRCV =
VXMT VT/R VT/R VRCV
12-2587.G (F)
BASIC TEST CIRCUIT
Figure 8. ac Gains
Figure 6. Longitudinal PSRR
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Thus, if the total power dissipated in the SLIC is less than 1.83 W, it will not enter the thermal shutdown state. Total SLIC power is calculated as: Total PD = maximum battery * maximum current limit + SLIC quiescent power. For the L9216, the worst-case SLIC on-hook active power is 75 mW. Thus, Total off-hook power = (ILOOP)(current-limit tolerance)*(VBATAPPLIED) + SLIC on-hook power Total off-hook power = (0.030 A)(1.08) * (21) + 75 mW Total off-hook power = 755.4 mW The power dissipated in the SLIC is the total power dissipation less the power that is dissipated in the loop. SLIC PD = total power - loop power Loop off-hook power = (ILOOP * 1.08)2 * (RLOOP(dc) min + 2RHANDSET) Loop off-hook power = (0.030 A)(1.08)2 * (20 + 60 + 200 ) Loop off-hook power = 293.9 mW SLIC off-hook power = Total off-hook power - loop off-hook power SLIC off-hook power = 755.4 mW - 293.9 mW SLIC off-hook power = 461.5 mW < 1.83 W Thus, under the operating conditions of this example, the thermal design, using the auxiliary, is adequate to ensure the device is not driven into thermal shutdown under worst-case operating conditions.
Applications
Power Control
Under normal device operating conditions, power dissipation on the device must be controlled to prevent the device temperature from rising above the thermal shutdown and causing the device to shut down. Power dissipation is highest with higher battery voltages, higher current limit, and under shorter dc loop conditions. Additionally, higher ambient temperature will also reduce thermal margin. To support required power ringing voltages, this device is meant to operate with a high-voltage primary battery (-65 V to -75 V typically). Thus, power control is normally achieved by use of the battery switch and an auxiliary lower absolute voltage battery. Operating temperature range, maximum current limit, maximum battery voltage, minimum dc loop length and protection resistor values, airflow, and number of PC board layers will influence the overall thermal performance. The following example illustrates typical thermal design considerations. The thermal resistance of the 28-pin PLCC package is typically 35.5 C/W, which is representative of the natural airflow as seen in a typical switch cabinet with a multilayer board. The L9216 will enter thermal shutdown at a temperature of 150 C. The thermal design should ensure that the SLIC does not reach this temperature under normal operating conditions. For this example, assume a maximum ambient operating temperature of 85 C, a maximum current limit of 30 mA, a maximum battery of -75 V, and an auxiliary battery of -21 V. Assume a (worst-case) minimum dc loop of 20 of wire resistance, 30 protection resistors, and 200 for the handset. Additionally, include the effects of parameter tolerance. 1. TTSD - TAMBIENT(max) = allowed thermal rise. 150 C - 85 C = 65 C. 2. Allowed thermal rise = package thermal impedance * SLIC power dissipation. 65 C = 35.5 C/W * SLIC power dissipation SLIC power dissipation (PD) = 1.83 W.
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Overhead Voltage
Active Mode Overhead is fixed to a nominal 6.0 V, which is adequate for on-hook transmission of 3.14 dBm into 900 . Scan Mode If the magnitude of the primary battery is greater than 51 V, the magnitude of the open loop tip-to-ring open loop voltage is clamped typically between 44 V and 51 V. If the magnitude of the primary battery is less than a nominal 51 V, the overhead voltage will track the magnitude of the battery voltage, i.e., the magnitude of the open circuit tip-to-ring voltage will be 4 V to 6 V less than battery. In the scan mode, overhead is unaffected by VOVH. On Hook Transmission Mode If the magnitude of the primary battery is greater than 51 V, the magnitude of the open loop tip-to-ring open loop voltage is clamped typically between 41 V and 49 V. If the magnitude of the primary battery is less than a nominal 51 V, the overhead voltage will track the magnitude of the battery voltage, i.e., the magnitude of the open circuit tip-to-ring voltage will be 6 V to 8 V less than battery. In the scan mode, overhead is unaffected by VOVH.
Applications (continued)
dc Loop Current Limit
Current limit may be chosen from two discrete values, 25 mA or 40 mA, depending on if VPROG is grounded (25 mA) or left floating (40 mA). Note that there is a 12.5 k slope to the I/V characteristic in the currentlimit region; thus, once in current limit, the actual loop current will increase slightly, as loop length decreases. The above describes the active mode steady-state current-limit response. There will be a transient response of the current-limit circuit upon an on- to off-hook transition. Typical active mode transient current-limit response is given in Table 19. Table 19. Typical Active Mode On- to Off-Hook Tip/ Ring Current-Limit Transient Response Parameter dc Loop Current: Active Mode RLOOP = 100 On- to Off-hook Transition t < 5 ms dc Loop Current: Active Mode RLOOP = 100 On- to Off-hook Transition t < 50 ms dc Loop Current: Active Mode RLOOP = 100 On- to Off-hook Transition t < 300 ms Value ILIM + 60 Unit mA
ILIM + 20
mA
ILIM
mA
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Applications (continued)
Overhead Voltage (continued)
Ring Mode In the ring mode, to maximize ringing loop length, the overhead is decreased to the saturation of the tip ring drive amplifiers, a nominal 4 V. The tip to ground voltage is 1 V, and the ring to VBAT1 voltage is 3 V. During the ring mode, to conserve power, the receive input at RCVN/RCVP is deactivated. During the ring mode, to conserve power, the AAC amplifier in the transmit direction at VITR is deactivated. However, if the AX amplifier at VTX is active during the ring mode, differential ring current may be sensed at VTX during the ring mode.
Supervision
The L9216 offers the loop closure and ring trip supervision functions. Internal to the device, the outputs of these detectors are multiplexed into a single package output, NSTAT. Additionally, a common-mode current detector for tip or ring ground detection is included for ground key applications.
Loop Closure
The loop closure has a fixed typical 10.5 mA on- to offhook threshold in the active mode and a fixed 11.5 mA on- to off-hook threshold from the scan mode. In either case, there is a 2 mA hysteresis with VCC = 5 V and a 1 mA hysteresis with VCC = 3.3 V.
Loop Range
The dc loop range is calculated using: VBAT2 - VOH RL = -------------------------------------- - 2RP - RDC ILIMIT VBAT2 is typically applied under off-hook conditions for power conservation and SLIC thermal considerations. The L9216 is intended for short-loop applications and, therefore, will always be in current limit during off-hook conditions. However, note that the ringing loop length rather than the dc loop length, will be the factor to determine operating loop length.
Ring Trip
The ring trip detector requires only a single-pole filter at the input, minimizing external components. An R/C combination of 383 k and 0.1 F, for a filter pole at 5.15 Hz, is recommended. The ring trip threshold is internally fixed as a function of battery voltage and is given by: RT (mA) = 67 * {(0.0045 * VBAT1) + 0.317} where: RT is ring trip current in mA. VBAT1 is the magnitude of the ring battery in V. There is a 6 mA to 8 mA hysteresis.
Battery Reversal Rate
The rate of battery reverse is controlled or ramped by capacitors FB1 and FB2. Table 20 below shows FB1 and FB2 values vs. typical ramp time. Leave FB1 and FB2 open if it is not desired to ramp the rate of battery reversal. Table 20. FB1 and FB2 Values vs. Typical Ramp Time CFB1 and CFB2 0.01 F 0.1 F 0.22 F 0.47 F 1.0 F 1.22 F 1.3 F 1.4 F 1.6 F 24 Transition Time 20 ms 220 ms 440 ms 900 ms 1.8 s 2.25 s 2.5 s 2.7 s 3.2 s
Tip or Ring Ground Detector
In the ground key or ground start applications, a common-mode current detector is used to indicate either a tip- or ring-ground has occurred (ground key) or an offhook has occurred (ground start). For ground start applications detection may be seen at the output of the common mode current detector (RGDET) or the loop closure detector (NSTAT). If ICM is used, the detection threshold is set by connecting a resistor from ICM to VCC. 205 x VCC/RICM (k) = ITH (mA) Additionally, a filter capacitor across RICM will set the time constant of the detector. No hysteresis is associated with this detector. The RC filter at ICM gives immunity to longitudinal currents.
Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Supervision (continued)
80
Tip or Ring Ground Detector (continued)
Also in the ground start mode, the fixed loop current threshold associated with the NSTAT detector output is internally adjusted to account for common-mode current detection in ground start mode (as opposed to differential current in loop start mode) maintain the detector at 10 mA. Thus, NSTAT may also be used for loop closure detion in ground start. However, the detector at NSTAT is not filtered against longitudinal currents, which may or may not be an issue in short loop applications. Using NSTAT will also save components at ICM.
VOLTS (V)
60 40 20 0 -20 -40 -60 -80 0.00 0.04 0.08 0.12 0.16 0.20 0.02 0.06 0.10 0.14 0.18 TIME (s)
12-3346a (F)
Note: Slew rate = 5.65 V/ms; trise = tfall = 23 ms; pwidth = 2 ms; period = 50 ms.
Power Ring
The device offers a ring mode, in which a balanced power ring signal is provided to the tip/ring pair. During the ring mode, a user-supplied low-voltage ring signal is input to the device's RINGIN input. This signal is amplified to produce the balanced power ring signal. The user may supply a sine wave input, PWM input, or a square wave to produce sinusoidal or trapezoidal ringing at tip and ring. Various crest factors are shown for illustrative purposes.
Figure 9. Ringing Waveform Crest Factor = 1.6
80 60 VOLTS (V) 40 20 0 -20 -40 -60 -80 0.00 0.04 0.08 0.12 0.16 0.20 0.02 0.06 0.10 0.14 0.18 TIME (s)
12-3347a (F)
Note: Slew rate = 10.83 V/ms; trise = tfall = 12 ms; pwidth = 13 ms; period = 50 ms.
Figure 10. Ringing Waveform Crest Factor = 1.2 Voltage applied to the load may be increased by using a filtered square wave input to produce a lower crest factor trapezoidal power ring signal at tip and ring.
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
on ring and from -8 V to -34 V on tip, as shown in Figure 11. Thus, the total voltage swing is 52 V (60 V to 8 V) for a 1 V input, which is approximately the differential gain of the device. Note that the tip and ring power ring signals will swing around VBATTERY divided by two. In this case, there is a -70 V battery so tip and ring swing around -34 V.
0 VRING VTIP
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring Signal Output The low-voltage sine wave input is applied to the L9216 at pin RINGIN. This signal should be ac-coupled through 0.47 F. During the ring mode, the signal at RINGIN is amplified and presented to the subscriber loop. The differential gain from RINGIN to tip and ring is a nominal 55. When the device enters the ring mode, the tip/ring overhead set at OVH and the scan clamp circuit is disabled, allowing the voltage magnitude of the power ring signal to be maximized. Additionally, in the ring mode, the loop current limit is increased 2.5X the value set by the VPROG voltage. The magnitude of the power ring voltage will be a function of the gain of the ring amplifier, the high voltage battery, and the input signal at RINGIN. The input range of the signal at RINGIN is 0 V to Vcc. As the input voltage at RINGIN is increased, the magnitude of the power ring voltage at tip and ring will increase linearly, per the differential gain of 55, until the tip and ring drive amplifiers begin to saturate. Once the tip and ring amplifiers reach saturation, further increases of the input signal will cause clipping distortion of the power ring signal at tip and ring. The ring signal will appear balanced on tip and ring. That is, the power ring signal is applied to both tip and ring, with the signal on tip 180 (180 degrees) out of phase from the signal on ring. Figure 11 shows typical operation of the ring mode, prior to saturation of the tip and ring drive amplifiers. A -70 V battery is used with a 100 loop and a 1 REN load. The input signal is 1 V through a 0.47 F capacitor at RINGIN, (the input circuit is shown in Figure 12). This produces a voltage swing from -34 V to -60 V
-20
-40
-60 0.60 0.62 0.64 0.66 0.68 0.70 TIME 12-3573F 1.0 VRINGIN 0.72 0.74 0.76 0.78 0.80
0.5
0.0
-0.5
-1.0 0.60 0.62 0.64 0.66 0.68 0.70 TIME 12-3574F 0.72 0.74 0.76 0.78 0.80
Figure 11. Ring Mode Typical Operation
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued) It is recommended that the input level at RINGIN be adjusted so that the power ring signal at tip and ring is just at the edge or slightly clipping. This gives maximum power transfer with minimal distortion of the sine wave. The tip side will saturate at a nominal 1 V above ground. The ring side will saturate at a nominal 3 V above battery. The input circuit for a sine wave along with waveforms to illustrate the tip and ring saturation is shown in Figure 12.
L9216
GND 1V VTIP 71 V 3V VBAT VRING
PT
+1 RINGIN 0.47 F 27.5x INPUT
TR
-1 100 k
VBAT = -75 V
12-3532J
Figure 12. RINGIN Operation The point at which clipping of the power ring signal begins at tip and ring is a function of the battery voltage, the input capacitor at RINGIN, and the input signal at RINGIN and Vcc. Typical characteristic conditions showing the onset of clipping are given below. Table 21. Onset of Power Ringing Clipping VCC = 5 V, Cinput = 0.47 F Input VBAT1 (V) -70.15 -68.06 -66.00 -64.08 -62.04 -60.05 Vrms (mV) 891 858 833 814 789 747 Vrms (V) 46.88 45.11 43.69 42.57 41.21 39.11 T/R Gain 52.62 52.58 52.45 52.30 52.23 52.36
Table 22. Onset of Power Ringing Clipping VCC = 3.1 V, Cinput = 0.47 F Input VBAT1 (V) -70.12 -68.07 -66.06 -64.01 -62.00 -60.00 Vrms (mV) 894 855 824 799 780 749 Vrms (V) 47.15 45.11 43.38 41.95 40.79 39.09 T/R Gain 52.74 52.76 52.65 52.5 52.29 52.19
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Supervision (continued)
Power Ring (continued)
Sine Wave Input Signal and Sine Wave Power Ring Signal Output (continued) During nonring modes, the sinusoidal ringing waveform may be left on at RINGIN. Via the state table, the ring signal will be removed from tip and ring even if the low- voltage input is still present at RINGIN. There are certain timing considerations that should be made with respect to state changes which are detailed in the Switching Behavior of L9215/6 Ringing SLIC Application Note. PWM Input Signal and Sine Wave Power Ring Signal Output A pulse-width modulated (PWM) signal may be used to provide the ringing input to RINGIN. The signal is applied through a low-pass filter and ac-coupled into RINGIN as shown in Figure 13 below. This approach gives a sine wave output at tip and ring.
L9215/16 R1 INPUT C1 C2 RINGIN
12-3578bF
Figure 13. L9215/16 Ringing Input Circuit Selection Table for Square Wave and PWM Inputs Table 23. Signal and Component Selection Chart VBAT 70 V 70 V 70 V 70 V 70 V 70 V 85 V 85 V 85 V 85 V 85 V 85 V VCC 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V Input 5 V Square 3 V Square 10 kHz PWM 5 V 10 kHz PWM 3 V 90 kHz PWM 5 V 90 kHz PWM 3 V 5 V Square 3 V Square 10 kHz PWM 5 V 10 kHz PWM 3 V 90 kHz PWM 5 V 90 kHz PWM 3 V R1 12 k 7 k 10 k 10 k 7 k 7 k 10 k 7 k 10 k 4 k 4 k 4 k C1 1 F 1 F 0.22 F 0.22 F 0.1 F 0.1 F 1 F 1 F 0.22 F 0.22 F 0.1 F 0.1 F C2 0.47 F 0.47 F 0.47 F 0.47 F 0.47 F 0.47 F 0.47 F 0.47 F 0.47 F 0.47 F 0.47 F 0.47 F CF 1.3 1.3 sine sine sine sine 1.3 1.3 sine sine sine sine Typical 5 REN Ringing Voltage RMS 48 V 49 V 42 V 42 V 42 V 42 V 59 V 51 V 51 V 47 V 51 V 49 V
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Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
5 V VCC Operation A PWM signal was generated with an HPTM 8116 Function Generator modulated with a 20 Hz signal. The optimal frequency used was 10 kHz. The PWM signal amplitude was 5.0 V (0 V to 5 V). This signal is shown in Figure 15.
Supervision (continued)
Power Ring (continued)
PWM Input Signal and Sine Wave Power Ring Signal Output (continued) Modulation waveforms showing PWM are in Figure 14 below.
12-3575F
Figure 15. 5 V PWM Signal Amplitude
12-3381(F)
A. Upper = Pwm Signal Centered at 10 kHz Lower = Modulation Signal
This input produced 44.96 Vrms ringing signal on tip/ring under open-loop conditions and 42.0 Vrms was delivered to 5 REN load. The ringing output on ring, with VCC = 5 V, is shown in Figure 16.
12-3380(F)
B. Same as A but Expanded Figure 14. Modulation Waveforms
1660
Notes: The modulating 20 Hz signal THD was measured at 1.3%. The tip/ring 20 Hz signal THD was measured at 1%. VBAT1 = -70.6 V, VBAT2 = -26.5 V, VCC = 5.019 V. PWM input 10 kHz, 5.0 Vp-p. R1 = 10 k, C1 = 0.22 F, C2 = 0.47 F.
Figure 16. Ringing Output on RING, with VCC = 5 V
Agere Systems Inc.
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
During nonring modes, the PWM waveform may be left on at RINGIN. Via the state table, the ring signal will be removed from tip and ring even if the low-voltage input is still present at RINGIN. There are certain timing considerations that should be made with respect to state changes which are detailed in the Switching Behavior of L9215/6 Ringing SLIC Application Note. Square Wave Input Signal and Trapezoidal Power Ring Signal Output A low-voltage square wave signal may be used to provide the ringing input to RINGIN. The signal is applied through a low-pass filter and ac-coupled into RINGIN as shown in Figure 13 and Table 23. This approach gives a trapezoidal wave output at tip and ring. Using this approach, a trapezoidal waveform can be achieved at tip and ring. This has the advantage of increasing the power transfer to the load for a given battery voltage, thus increasing the effective ringing loop length as compared to a sine wave. The actual crest factor achieved is a function of the magnitude of the battery, the magnitude of the input voltage, frequency, and R1.
Supervision (continued)
Power Ring (continued)
3.3 V VCC Operation A PWM signal was generated with an HP 8116 Function Generator modulated with a 20 Hz signal. The optimal frequency used was 10 kHz. The PWM signal amplitude was 3.10 V (0 V to 3.10 V). This input signal is shown in Figure 17.
12-3571F
Figure 17. 3.3 V PWM Signal Amplitude This produced 44.96 Vrms ringing signal on tip/ring under open-loop conditions and 42.0 Vrms was delivered to 5 REN load. The ringing output on ring with VCC = 3.1 V is shown in Figure 18.
CH1
CH2
CH3
CH4
1660
Notes: The modulating 20 Hz signal THD was measured at 1.3%. The tip/ring 20 Hz signal THD was measured at 1%. VBAT1 = -70.6 V, VBAT2 = -26.5 V, VCC = 3.10 V. PWM input 10 kHz, 3.1 Vp-p. R1 = 10 k, C1 = 0.22 F, C2 = 0.47 F.
12-3572F
Notes: CH1--CMOS Input (5 V) at RINGIN. CH2--Filtered input at RINGIN. CH3--Tip. CH4--Ring. R1 = 14 k, C1 = 1.0 F, C2 = 0.47 F. VBAT1 = -70 V, Vrms = 51 V, Vp-p = 67 V, frequency = 20 Hz, Crest Factor = 1.3.
Figure 18. Ringing Output on RING, with VCC = 3.1 V
Figure 19. Square Wave Input Signal and Trapezoidal Power Ring Signal Output
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Supervision (continued)
Power Ring (continued)
Square Wave Input Signal and Trapezoidal Power Ring Signal Output (continued) Figure 20 and Figure 21 provide some guidance to the relationship between crest factor, battery voltage, and R1 value.
1.36 1.35 1.34 1.33 1.32 CF 1.31 1.3 1.29 1.28 1.27 1.26 58 60 62 64 BAT V
12-3576F
66
68
70
72
Figure 20. Crest Factor vs. Battery Voltage
1.5
1.45
1.4 CF 1.35 1.3 1.25 10 10.5 11 11.5 12 R (k) 12.5 13 13.5 14
12-3577F
Figure 21. Crest Factor vs. R (k) During nonring modes, the square wave input may be left on or removed from RINGIN. Via the state table, the ring signal will be removed from tip and ring even if the low-voltage input is still present at RINGIN. However, removing the waveform has certain advantages in terms of the timing of state. These advantages are detailed in the Switching Behavior of L9215/16 Ringing SLIC Application Note.
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Third-Generation Codecs This class of devices includes all ac parameters set digitally under microprocessor control. Depending on the device, it may or may not have data control latches. Additional functionality sometimes offered includes tone plant generation and reception, PPM generation, test algorithms, and echo cancellation. Again, this type of codec may be 3.3 V, 5 V only, or 5 V operation, single quad or multichannel, and -law/A-law or 16-bit linear coding selectable. Examples of this type of codec are the Agere T8535/6 (5 V only, quad, standard features), T8537/8 (3.3 V only, quad, standard features), T8533/4 (5 V only, quad with echo cancellation), and the T8531/32 (5 V only multichannel).
ac Applications
ac Parameters
There are four key ac design parameters. Termination impedance is the impedance looking into the 2-wire port of the line card. It is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. Transmit gain is measured from the 2-wire port to the PCM highway, while receive gain is done from the PCM highway to the transmit port. Transmit and receive gains may be specified in terms of an actual gain, or in terms of a transmission level point (TLP), that is the actual ac transmission level in dBm. Finally, the hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port.
ac Interface Network
The ac interface network between the L9216 and the codec will vary depending on the codec selected. With a first-generation codec, the interface between the L9216 and codec actually sets the ac parameters. With a third-generation codec, all ac parameters are set digitally, internal to the codec; thus, the interface between the L9216 and this type of codec is designed to avoid overload at the codec input in the transmit direction and to optimize signal to noise ratio (S/N) in the receive direction. Because the design requirements are very different with a first- or third-generation codec, the L9216 is offered with two different receive gains. Each receive gain was chosen to optimize, in terms of external components required, the ac interface between the L9216 and codec.
Codec Types
At this point in the design, the codec needs to be selected. The interface network between the SLIC and codec can then be designed. Below is a brief codec feature summary. First-Generation Codecs These perform the basic filtering, A/D (transmit), D/A (receive), and -law/A-law companding. They all have an op amp in front of the A/D converter for transmit gain setting and hybrid balance (cancellation at the summing node). Depending on the type, some have differential analog input stages, differential analog output stages, 5 V only or 5 V operation, and -law/A-law selectability. These are available in single and quad designs. This type of codec requires continuous time analog filtering via external resistor/capacitor networks to set the ac design parameters. An example of this type of codec is the Agere T7504 quad 5 V only codec. This type of codec tends to be the most economical in terms of piece part price, but tends to require more external components than a third-generation codec. Further ac parameters are fixed by the external R/C network so software control of ac parameters is difficult.
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Note also that some third-generation codecs require the designer to provide an inherent resistive termination via external networks. The codec will then provide gain shaping, as a function of frequency, to meet the return loss requirements. This feedback will increase the signal at the codec input and increase the likelihood that a resistor divider is needed in the transmit direction. Further stability issues may add external components or excessive ground plane requirements to the design. In the receive direction, the issue is to optimize the S/N. Again, the designer must consider all the considered TLPs. The idea, for all desired TLPs, is to run the codec at or as close as possible to its maximum output signal, to optimize the S/N. Remember, noise floor is constant, so the hotter the signal from the codec, the better the S/N. The problem is if the codec is feeding a high gain SLIC, either an external resistor divider is needed to knock the gain down to meet the TLP requirements, or the codec is not operated near maximum signal levels, thus compromising the S/N. Thus, it appears that the solution is to have a SLIC with a low gain, especially in the receive direction. This will allow the codec to operate near its maximum output signal (to optimize S/N), without an external resistor divider (to minimize cost). To meet the unique requirements of both types of codecs, the L9216 offers two receive gain choices. These receive gains are mask-programmable at the factory and are offered as two different code variations. For interface with a first-generation codec, the L9216 is offered with a receive gain of 8. For interface with a third-generation codec, the L9216 is offered with a receive gain of 2. In either case, the transconductance in the transmit direction or the transmit gain is 300 . These receive gain options afford the designer the flexibility to maximize performance and minimize external components, regardless of the type of codec chosen.
ac Applications (continued)
ac Interface Network (continued)
With a first-generation codec, the termination impedance is set by providing gain shaping through a feedback network from the SLIC VITR output to the SLIC RCVN/RCVP inputs. The L9216 provides a transconductance from T/R to VITR in the transmit direction and a single-ended to differential gain from either RCVN or RCVP to T/R in the receive direction. Assuming a short from VITR to RCVN or RCVP, the maximum impedance that is seen looking into the SLIC is the product of the SLIC transconductance multiplied by the SLIC receive gain, plus the protection resistors. The various specified termination impedances can range over the voiceband as low as 300 up to over 1000 . Thus, if the SLIC gains are too low, it will be impossible to synthesize the higher termination impedances. Further, the termination that is achieved will be far less than what is calculated by assuming a short for SLIC output to SLIC input. In the receive direction, in order to control echo, the gain is typically a loss, which requires a loss network at the SLIC RCVN/RCVP inputs, which will reduce the amount of gain that is available for termination impedance. For this reason, a high-gain SLIC is required with a first-generation codec. With a third-generation codec, the line card designer has different concerns. To design the ac interface, the designer must first decide upon all termination impedance, hybrid balances, and transmission level point (TLP) requirements that the line card must meet. In the transmit direction, the only concern is that the SLIC does not provide a signal that is too hot and overloads the codec input. Thus, for the highest TLP that is being designed to, given the SLIC gain, the designer, as a function of voiceband frequency, must ensure the codec is not overloaded. With a given TLP and a given SLIC gain, if the signal will cause a codec overload, the designer must insert some sort of loss, typically a resistor divider, between the SLIC output and codec input.
Agere Systems Inc.
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Receive Gain: VT/R grcv = ----------VFR grcv = 8 -----------------------------------------------------------------ZT 1 + RRCV + RRCV 1 + -------- - ----------- ----------- RT1 RGP ZT/R
ac Applications (continued)
Design Examples
First-Generation Codec ac Interface Network-- Resistive Termination The reference circuit in Figure 23 shows the complete SLIC schematic for interface to the Agere T7504 firstgeneration codec for a resistive termination impedance. For this example, the ac interface was designed for a 600 resistive termination and hybrid balance with transmit gain and receive gain set to 0 dBm. This is a lower feature application example and uses single battery operation, fixed overhead, current limit, and loop closure threshold. Resistor RGN is optional. It compensates for any mismatch of input bias voltage at the RCVN/RCVP inputs. If it is not used, there may be a slight offset at tip and ring due to mismatch of input bias voltage at the RCVN/RCVP inputs. It is very common to simply tie RCVN directly to ground in this particular mode of operation. If used, to calculate RGN, the impedance from RCVN to ac ground should equal the impedance from RCVP to ac ground. Example 1, Real Termination The following design equations refer to the circuit in Figure 22. Use these to synthesize real termination impedance. Termination Impedance: VT/R zT = ------------ IT/R zT = 50 2400 + 2 RP + ---------------------------------RT1 1 + -------- + ----------- RT1RGP RRCV
Transmit Gain: gtx = VGSX ---------VT/R
gtx =
- RX x --------------- 300 RT2 ZT/R
Hybrid Balance: RX hbal = 20log ----------- - gtx x grcv RHB VGSX hbal = 20log -------------- VFR To optimize the hybrid balance, the sum of the currents at the VFX input of the codec op amp should be set to 0. The expression for ZHB becomes the following: RHB ( k ) = RX -----------------gtx x grcv
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued)
RX VGSX -0.300 V/mA RT2 VITR RCVN RCVP RGP + AV = -1 18 - L9216 1/4 T7504 CODEC
0586 (F)
VFXIN - VFXIP + +2.4 V VFR
ZT/R
RP TIP
18
- AV = 1 +
- AV = 4 +
RT1 RHB1 RRCV
VS
IT/R + ZT VT/R - RP RING
CURRENT SENSE
Figure 22. ac Equivalent Circuit
VBAT1 CBAT1
VBAT2 VCC CBAT2 CCC
DBAT1 0.1 F 0.1 F 0.1 F VBAT1 BGND VBAT2 VCC AGND CRT 0.1 F RRT 383 k FUSIBLE OR PTC 30 VBAT1
AGERE L7591
ICM
RGDET ITR RGX 4750 VTX RX CTX 0.1 F TXI RT6 49.9 k VITR CC1 0.1 F RHB1 VFXIN 100 k CC2 0.1 F - DX + +2.4 V VFRO DR FSE FSEP MCLK SYNC AND CLOCK PCM HIGHWAY
RTFLT
DCOUT PR
100 k
GSX
30 FUSIBLE OR PTC
PT
L9216A
RCVP
RT3 69.8 k RRCV 60.4 k
VPROG
RGP 26.7 k
rate of battery reversal not ramped CF2 FB1 FB2 NSTAT B2 B1 B0 RCVN VREF
VREF
RN2 17.65 k
RINGIN C2 0.47 F C1 1.0 F R1 12 k VREF ASEL
CF1 CF1
0.22 F
1/4 T7504 CODEC
CONTROL INPUTS
CF2 0.1 F
Figure 23. Agere T7504 First-Generation Codec Resistive Termination Agere Systems Inc. 35
L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
ac Applications (continued)
Design Examples (continued)
Example 1, Real Termination (continued) Table 24. Parts List L9216; Agere T7504 First-Generation Codec Resistive Termination; Nonmeter Pulse Application Name Value Fault Protection RPT 30 RPR 30 Protector Agere L7591 Power Supply CBAT1 0.1 F CBAT2 0.1 F DBAT1 1N4004 CCC 0.1 F CF1 0.22 F CF2 0.1 F Ring/Ring Trip C1 1.0 F C2 0.47 F R1 12 k CRT 0.1 F RRT 383 k ac Interface RGX 4750 CTX 0.1 F CC1 0.1 F CC2 0.1 F RT3 69.8 k RT6 RX RHB1 RRCV RGP RGN Optional 49.9 k 100 k 100 k 60.4 k 26.7 k 17.6 k Tolerance 1% 1% -- 20% 20% -- 20% 20% 20% 20% 20% 1% 20% 1% 1% 20% 20% 20% 1% 1% 1% 1% 1% 1% 1% Rating Function
Fusible or PTC Protection resistor. Fusible or PTC Protection resistor. -- Secondary protection. 100 V 50 V -- 10 V 100 V 100 V 10 V 10 V 1/16 W 10 V 1/16 W 1/16 W 10 V 10 V 10 V 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W VBAT filter capacitor. VBAT filter capacitor. |VBAT2| < |VBAT1|. Reverse current. VCC filter capacitor. Filter capacitor. Filter capacitor. Ring filter for square wave. ac-couple input ring signal. Ring filter for square wave. Ring trip filter capacitor. Ring trip filter resistor. Sets T/R to VITR transconductance. ac/dc separation. dc blocking capacitor. dc blocking capacitor. With RGP and RRCV, sets termination impedance and receive gain. With RX, sets transmit gain. With RT6, sets transmit gain. With RX, sets hybrid balance. With RGP and RT3, sets termination impedance and receive gain. With RRCV and RT3, sets termination impedance and receive gain. Optional. Compensates for input offset at RCVN/RCVP.
Notes: Termination Impedance = 600 . Hybrid Balance = 600 . Tx = 0 dBm. Rx = 0 dBm.
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
ac Interface Using First-Generation Codec RGX/RTGS/CGS (ZTG): these components give gain shaping to get good gain flatness. These components are a scaled version of the specified complex termination impedance. Note for pure (600 ) resistive terminations, components RTGS and CGS are not used. Resistor RGX is used and is still 4750 . RX/RT6: with other components set, the transmit gain (for complex and resistive terminations) RX and RT6 are varied to give specified transmit gain. RT3/RRCV/RGP: for both complex and resistive terminations, the ratio of these resistors sets the receive gain. For resistive terminations, the ratio of these resistors sets the return loss characteristic. For complex terminations, the ratio of these resistors sets the low-frequency return loss characteristic. CN/RN1/RN2: for complex terminations, these components provide high-frequency compensation to the return loss characteristic. For resistive terminations, these components are not used and RCVN is connected to ground via a resistor. RHB: sets hybrid balance for all terminations. Set ZTG--Gain Shaping: ZTG = RGX || RTGS + CGS which is a scaled version of ZT/R (the specified termination resistance) in the R1 || R2 + C form.
5-6396(F)
ac Applications (continued)
Design Examples (continued)
First-Generation Codec ac Interface Network-- Complex Termination The reference circuit in Figure 26 shows the complete SLIC schematic for interface to the Agere T7504 firstgeneration codec for the German complex termination impedance. For this example, the ac interface was designed for a 220 + (820 || 115 nF) complex termination and hybrid balance with transmit gain and receive gain set to 0 dBm. For illustration purposes, 1 Vrms PPM injection was assumed in this example. This implies the overhead voltage is increased to 7.24 V and no meter pulse rejection is required. Also, this example illustrates the device using fixed overhead and current limit. Complex Termination Impedance Design Example The gain shaping necessary for a complex termination impedance may be done by shaping across the AX amplifier at nodes ITR and VTX. Complex termination is specified in the form:
R2
R1 C
To work with this application, convert termination to the form:
R1
RGX must be 4750 to set SLIC transconductance to 300 V/A. RGX = 4750 At dc, CGS and C are open. RGX = M x R1
R2
C
5-6398(F)
where: R1 = R1 + R2 R1 R2 = ------- (R1 + R2) R2
2 R2 C = --------------------- C R1 + R2
where M is the scale factor. 4750 M = -------------R1 It can be shown: RTGS = M x R2 and CTGS = C ----M
Agere Systems Inc.
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Using REQ, calculate the desired transmit gain, taking into account the impedance transformation: 600 TX (dB) = TX (specified[dB]) + 20log ---------REQ TX (specified[dB]) is the specified transmit gain. 600 is the impedance at the PCM, and REQ is the impedance at 600 tip and ring. 20log ---------- represents the power REQ loss/gain due to the impedance transformation. Note that in the case of a 600 pure resistive termination 600 600 at T/R 20log ---------- = 20log --------- = 0. REQ 600 Thus, there is no power loss/gain due to impedance transformation and TX (dB) = TX (specified[dB]).
ac Applications (continued)
Design Examples (continued)
Transmit Gain Transmit gain will be specified as a gain from T/R to PCM, TX (dB). Since PCM is referenced to 600 and assumed to be 0 dB, and in the case of T/R being referenced to some complex impedance other than 600 resistive, the effects of the impedance transformation must be taken into account. Again, specified complex termination impedance at T/R is of the form:
R2
R1 C
5-6396(F)
Finally, convert TX (dB) to a ratio, gTX: TX (dB) = 20log gTX The ratio of RX/RT6 is used to set the transmit gain: RX RT6
---------- = gTX * -----------------
First, calculate the equivalent resistance of this network at the midband frequency of 1000 Hz. REQ = 2 ( 2 f ) 2 C1 2 R1R2 2 + R1 + R2 2 2 fR2 2 C1 ---------------------------------------------------------------------------- + -------------------------------------------------- 2 R2 2 C1 2 1 + ( 2 f ) 2 R2 2 C1 2 1 + ( 2 f )
318.25 20
1 * ---- with a quad Agere codec M
such as T7504: RX < 200 k
RTGS
CGS Rx
-IT/R 318.25
RGX = 4750 0.1 F 20 VTX TXI VITR RT6 - + CODEC OP AMP CN RN1 RCVN RCVP RN2 RRCV RGP RT3 RHB
CODEC OUTPUT DRIVE AMP
5-6400.P (F)
Figure 24. Interface Circuit Using First-Generation Codec (Blocking Capacitors Not Shown)
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Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Hybrid Balance Set the hybrid cancellation via RHB. RX RHB = -----------------------------gRCV x gTX If a 5 V only codec such as the Agere T7504 is used, dc blocking capacitors must be added as shown in Figure 25. This is because the codec is referenced to 2.5 V and the SLIC to ground--with the ac coupling, a dc bias at T/R is eliminated and power associated with this bias is not consumed. Typically, values of 0.1 F to 0.47 F capacitors are used for dc blocking. The addition of blocking capacitors will cause a shift in the return loss and hybrid balance frequency response toward higher frequencies, degrading the lower-frequency response. The lower the value of the blocking capacitor, the more pronounced the effect is, but the cost of the capacitor is lower. It may be necessary to scale resistor values higher to compensate for the low-frequency response. This effect is best evaluated via simulation. A PSPICE(R) model for the L9216 is available. Design equation calculations seldom yield standard component values. Conversion from the calculated value to standard value may have an effect on the ac parameters. This effect should be evaluated and optimized via simulation.
ac Applications (continued)
Design Examples (continued)
Receive Gain Ratios of RRCV, RT3, RGP will set both the low-frequency termination and receive gain for the complex case. In the complex case, additional high-frequency compensation, via CN, RN1, and RN2, is needed for the return loss characteristic. For resistive termination, CN, RN1, and RN2 are not used and RCVN is tied to ground via a resistor. Determine the receive gain, gRCV, taking into account the impedance transformation in a manner similar to transmit gain. REQ RX (dB) = RX (specified[dB]) + 20log ---------600 RX (dB) = 20log gRCV Then: 4 gRCV = ----------------------------------------------RRCV RRCV 1 + --------------- + --------------RT3 RGP and low-frequency termination 2400 ZTER(low) = -------------------------------------------- + 2RP + 50 RT3 RT3 1 + ----------- + --------------RGP RRCV ZTER(low) is the specified termination impedance assuming low frequency (C or C is open). RP is the series protection resistor. 50 is the typical internal feed resistance. These two equations are best solved using a computer spreadsheet. Next, solve for the high-frequency return loss compensation circuit, CN, RN1, and RN2: 2RP CNRN2 = ------------ CG RTGP 2400 2400 RTGS RN1 = RN2 ------------ ------------- - 1 2RP RTGP There is an input offset voltage associated with nodes RCVN and RCVP. To minimize the effect of mismatch of this voltage at T/R, the equivalent resistance to ac ground at RCVN should be approximately equal to that at RCVP. Refer to Figure 25 (with dc blocking capacitors). To meet this requirement, RN2 = RGP || RT3.
Agere Systems Inc.
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
ac Applications (continued)
Design Examples (continued)
Blocking Capacitors
RTGS CGS Rx -IT/R 318.25 RGX = 4750 0.1 F 20 VTX TXI VITR RT6 CB1 - + CODEC OP AMP CN RN1 RCVN RCVP RN2 RRCV RGP RT3 RHB
CB2 2.5 V
CODEC OUTPUT DRIVE AMP
5-6401.M (F)
Figure 25. ac Interface Using First-Generation Codec (Including Blocking Capacitors) for Complex Termination Impedance
VBAT1 CBAT1 DBAT1 CRT 0.1 F RRT 383 k FUSIBLE OR PTC 30 VBAT1
AGERE L7591
VBAT2 VCC CBAT2 0.1 F CCC 0.1 F AGND ICM RGDET
ground key not used
0.1 F
VBAT1 RTFLT
BGND
VBAT2 VCC
ITR RGX 4750 VTX RTGS 1.74 k CGS 12 nF
DCOUT PR TXI
CTX 0.1 F CC1 RT6 40.6 k 0.1 F
RX 115 k GSX
30 FUSIBLE OR PTC
PT
L9216A
VITR
CN 120 pF
VFXIN RT3 RHB1 49.9 k 113 k RRCV
- DX + +2.4 VFRO DR FSE FSEP MCLK SYNC AND CLOCK PCM HIGHWAY
VPROG
RCVP RN1 127 k
59.0 k
CC2 0.1 F
VREF
rate of battery reversal not ramped
RCVN
RGP 54.9 k VREF RN2 47.5 k VREF
CF1 CF1
CF2
FB1 FB2
NSTAT
B2
B1
B0
RINGIN CRING 0.47 F RING
ASEL
CONTROL INPUTS
0.22 F
CF2 0.1 F
FROM/TO CONTROL
1/4 T7504 CODEC
Figure 26. Agere T7504 First-Generation Codec Complex Termination 40 Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
ac Applications (continued)
Design Examples (continued)
Blocking Capacitors (continued) Table 25. Parts List L9216; Agere T7504 First-Generation Codec Complex Termination; Meter Pulse Application Termination impedance = 220 + (820 || 115 nF), hybrid balance = 220 + (820 || 115 nF) Tx = 0 dBm, Rx = 0 dBm. Name Value Tolerance Rating Fault Protection RPT 30 1% Fusible or PTC RPR 30 1% Fusible or PTC Protector Agere -- -- L7591 Power Supply CBAT1 0.1 F 20% 100 V CBAT2 0.1 F 20% 50 V DBAT1 1N4004 -- -- CCC 0.1 F 20% 10 V CF1 0.22 F 20% 100 V CF2 0.1 F 20% 100 V Ring/Ring Trip CRING 0.47 F 20% 10 V CRT 0.1 F 20% 10 V RRT 383 k 1% 1/16 W ac Interface RGX 4750 1% 1/16 W RTGS 1.74 k 1% 1/16 W CGS 12 nF 5% 10 V CTX 0.1 F 20% 10 V CC1 0.1 F 20% 10 V CC2 0.1 F 20% 10 V RT3 49.9 k 1% 1/16 W RT6 RX RHB1 RRCV RGP CN RN1 RN2 40.2 k 115 k 113 k 59.0 k 54.9 k 120 pF 127 k 47.5 k 1% 1% 1% 1% 1% 20% 1% 1% 1/16 W 1/16 W 1/16 W 1/16 W 1/16 W 10 V 1/16 W 1/16 W Function Protection resistor. Protection resistor. Secondary protection.
VBAT filter capacitor. VBAT filter capacitor. |VBAT2| < |VBAT1|. Reverse current. VCC filter capacitor. Filter capacitor. Filter capacitor. ac-couple input ring signal. Ring trip filter capacitor. Ring trip filter resistor. Sets T/R to VITR transconductance. Gain shaping for complex termination. Gain shaping for complex termination. ac/dc separation. dc blocking capacitor. dc blocking capacitor. With RGP and RRCV, sets termination impedance and receive gain. With RX, sets transmit gain. With RT6, sets transmit gain. With RX, sets hybrid balance. With RGP and RT3, sets termination impedance and receive gain. With RRCV and RT3, sets termination impedance and receive gain. High frequency compensation. High frequency compensation. High frequency compensation, compensate for dc offset at RCVP/RCVN.
Agere Systems Inc.
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L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network--Complex Termination The following reference circuit, Figure 27, shows the complete SLIC schematic for interface to the Agere T8536 third-generation codec. All ac parameters are programmed by the T8536. Note this codec differentiates itself in that no external components are required in the ac interface to provide a dc termination impedance or for stability. For illustration purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this example illustrates the device using programmable overhead and current limit. Please see the T8535/6 data sheet for information on coefficient programming.
VBAT1 CBAT1 DBAT1 CRT 0.1 F RRT 383 k FUSIBLE OR PTC 50 VBAT1 AGERE L7591 50 FUSIBLE OR PTC PT PR RTFLT 0.1 F
VBAT2 VCC CBAT2 0.1 F CCC 0.1 F AGND ICM RGDET
ground key not used
VBAT1
BGND
VBAT2 VCC
ITR RGX 4750 VTX CTX 0.1 F TXI CC1 0.1 F VITR VFXI RCIN 20 M RCVP RCVN VFROP VFRON DX0 DR0 DX1 DR1 PCM HIGHWAY
DCOUT
L9216G
VPROG
VREF CF1 CF1 0.22 F CF2
1/4 T8536/8
rate of battery reversal not ramped
FS NSTAT B2 B1 B0 RINGIN CRING 0.47 F B2 B1 SLIC4a SLIC3a SLIC2a DGND SLIC0a VDD BCLK
FB1
FB2
SYNC AND CLOCK
CF2 0.1 F
FROM/TO CONTROL
B0 NSTAT
VDD
Figure 27. Third-Generation Codec ac Interface Network; Complex Termination
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Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
ac Applications (continued)
Design Examples (continued)
Third-Generation Codec ac Interface Network--Complex Termination (continued) Table 26. Parts List L9216; Agere T8536 Third-Generation Codec ac and dc Parameters; Fully Programmable Name Value Fault Protection RPT 50 RPR 50 Protector Agere L7591 Power Supply CBAT1 0.1 F CBAT2 0.1 F DBAT1 1N4004 CCC 0.1 F CF1 0.22 F CF2 0.1 F Ring/Ring Trip CRING 0.47 F CRT 0.1 F RRT 383 k ac Interface RGX 4750 RCIN 20 M CTX 0.1 F CC1 0.1 F Tolerance 1% 1% -- 20% 20% -- 20% 20% 20% 20% 20% 1% 1% 5% 20% 20% Rating Fusible or PTC Protection resistor*. Fusible or PTC Protection resistor*. -- Secondary protection. 100 V 50 V -- 10 V 100 V 100 V 10 V 10 V 1/16 W 1/16 W 1/16 W 10 V 10 V VBAT filter capacitor. VBAT filter capacitor. |VBAT2| < |VBAT1|. Reverse current. VCC filter capacitor. Filter capacitor. Filter capacitor. ac-couple input ring signal. Ring trip filter capacitor. Ring trip filter resistor. Sets T/R to VITR transconductance. dc bias. ac/dc separation. dc blocking capacitor. Function
* For loop stability, increase to 50 minimum if synthesizing 900 or 900 + 2.16 F termination impedance.
Agere Systems Inc.
43
L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Outline Diagrams
28-Pin PLCC
Dimensions are in millimeters. Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Sales Representative.
12.446 0.127 11.506 0.076 PIN #1 IDENTIFIER ZONE
4 1 26
5
25
11.506 0.076 12.446 0.127
11
19
12
18
4.572 MAX SEATING PLANE 1.27 TYP 0.51 MIN TYP 0.330/0.533
5-2506r.8(F)
0.10
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Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Outline Diagrams (continued)
48-Pin MLCC
Dimensions are in millimeters. Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Sales Representative. The exposed pad on the bottom of the package will be at VBAT1 potential.
7.00 3.50 6.75 3.375 0.50 BSC
1 2 3
C
C CL
PIN #1 IDENTIFIER ZONE
6.75 7.00
DETAIL A VIEW FOR EVEN TERMINAL/SIDE
0.18/0.30
0.00/0.05 SECTION C-C DETAIL A 12 SEATING PLANE 0.20 REF 11 SPACES @ 0.50 = 5.50 0.24/0.60 0.18/0.30 0.08 0.01/0.05 0.65/0.80 1.00 MAX
0.24/0.60
5.10 0.15
3 2 1
0.30/0.45 EXPOSED PAD 0.50 BSC
0195mod
Agere Systems Inc.
45
L9216A/G Short-Loop Ringing SLIC with Ground Start
Preliminary Data Sheet September 2001
Outline Diagrams (continued)
48-Pin MLCC, JEDEC MO-220 VKKD-2
Dimensions are in millimeters. Notes: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Sales Representative. The exposed pad on the bottom of the package will be at VBAT1 potential.
7.00 3.50 PIN #1 IDENTIFIER ZONE
CL
0.50 BSC 3.50 INDEX AREA (7.00/2 x 7.00/2) 7.00 DETAIL A VIEW FOR EVEN TERMINAL/SIDE
0.18
0.23
TOP VIEW
1.00 MAX SEATING PLANE 0.20 REF 0.08 0.02/0.05 DETAIL B 0.23
0.18
SIDE VIEW
11 SPACES @ 0.50 = 5.50 DETAIL A 0.18/0.30
0.30/0.50
2.50/2.625 5.00/5.25
3 2 1
EXPOSED PAD 0.50 BSC DETAIL B
BOTTOM VIEW
0195a
46
Agere Systems Inc.
Preliminary Data Sheet September 2001
L9216A/G Short-Loop Ringing SLIC with Ground Start
Ordering Information
Device Part No. LUCL9216AGF-D LUCL9216AGF-DT LUCL9216GGF-D LUCL9216GGF-DT LUCL9216ARG-D LUCL9216GRG-D Description SLIC Gain = 8 SLIC Gain = 8 SLIC Gain = 2 SLIC Gain = 2 SLIC Gain = 8 SLIC Gain = 2 Package 28-Pin PLCC Dry-bagged 28-Pin PLCC Tape & Reel, Dry-bagged 28-Pin PLCC Tape & Reel 28-Pin PLCC Tape & Reel, Dry-bagged 48-Pin MLCC Dry-bagged 48-Pin MLCC Dry-bagged Comcode 108876723 108876731 108876780 108876798 108955477 108955469
Agere Systems Inc.
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IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. PSPICE is a registered trademark of MicroSim Corporation. Telcordia Technologies is a trademark of Bell Communications Research, Inc. HP is a trademark of Hewlett-Packard Company.
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright (c) 2001 Agere Systems Inc. All Rights Reserved
September 2001 DS01-301ALC (Replaces DS00-133ALC)

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